1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of forming an interconnection line in a semiconductor device.
2. Description of the Related Art
In order to produce large-scale integration of semiconductor devices, a size of a memory cell is rapidly decreasing. To facilitate this decrease in size, a multi-layered interconnection structure is being employed. Accordingly, a pitch between interconnection lines is decreased so that an aspect ratio of a contact hole for electrically connecting a lower conductive layer with an upper conductive layer is increased.
FIGS. 1 and 2 illustrate cross-sectional views of a conventional method of forming an interconnection line in a semiconductor device.
Referring to FIG. 1, a first interlayer insulating layer 102 is formed on a semiconductor substrate 100. A first photoresist pattern (not shown) having an opening of a predetermined size is formed on the first interlayer insulating layer 102. Using the first photoresist pattern as an etch mask, an exposed portion of the first interlayer insulating layer 102 is anisotropically etched to form a contact hole 104. After forming the contact hole 104, the first photoresist pattern is removed. A native oxide layer formed on a portion of the semiconductor substrate 100 exposed through the contact hole 104 is then removed by wet etching. The wet etching is generally performed using a chemical solution containing hydrogen fluoride (HF). As a result of the wet etching, the first interlayer insulating layer 102 forming a sidewall of the contact hole 104, as well as the native oxide layer formed on the semiconductor substrate 100, is etched. Resultantly, the contact hole 104 has an opening larger than that of the contact hole 104 primarily formed by the anisotropic etching.
After performing the wet etching, a conductive layer, e.g., a polysilicon layer, is formed on the entire surface of the semiconductor substrate 100, thereby filling the contact hole 104. The conductive layer is then processed by chemical mechanical polishing (CMP) until the first interlayer insulating layer 102 is exposed, thereby forming a contact plug 106 in the contact hole 104.
Referring to FIG. 2, a second interlayer insulating layer 108 is formed on the contact plug 106 and the first interlayer insulating layer 102. A second photoresist pattern (not shown) having an opening of a predetermined size is formed on the second interlayer insulating layer 108. Using the second photoresist pattern as an etch mask, the second interlayer insulating layer 108 is etched to form an interconnection line groove 110 therein. After forming the interconnection line groove 110, the second photoresist pattern is removed and a conductive layer, e.g., tungsten (W), is formed to fill the interconnection line groove 110. The conductive layer is then processed by CMP until the second interlayer insulating layer 108 is exposed, so that a metal interconnection line 112 is formed in the second interlayer insulating layer 108, wherein the metal interconnection line 112 electrically contacts an upper surface of the contact plug 106.
In this conventional method of forming an interconnection line in a semiconductor device, the opening of the contact hole 104 is enlarged during the wet etching to remove the native oxide layer, so that an interval between the contact plugs 106 is decreased, as shown in FIG. 1. Therefore, a misalign margin of a photolithography process for forming the metal interconnection line 112 is reduced, so that a bridge may be formed by the metal interconnection line 112, as shown in FIG. 2, between adjacent contact plugs 106.
Further, in a case where the first interlayer insulating layer 102 within the contact hole 104 is excessively etched during the wet etching, adjacent contact plugs 106 may form a short circuit because nodes of the contact plugs 106 are not insulated during the CMP for forming the contact plug 106.
In an effort to solve the foregoing problems, formation of a silicon nitride spacer on sidewalls of the contact hole after formation of the contact hole has been proposed. The silicon nitride spacer is intended to prevent the interlayer insulating layer forming the sidewalls of the contact hole from being etched during the wet etching. Disadvantageously, however, silicon oxide (SiO2), which forms the interlayer insulating layer, has a dielectric constant of about four, while silicon nitride (SiN), which forms the spacer, has a dielectric constant of about nine. Accordingly, when the silicon nitride spacer is formed on the sidewalls of the contact hole and then the contact plug is formed in the contact hole, a loading capacitance between adjacent contact plugs is increased. Too great of a loading capacitance causes a reduction in an operating speed of the semiconductor device. In addition, because the interval between the contact plugs is reduced as the semiconductor devices are trending toward large-scale integration, the loading capacitance is further increased by the silicon nitride spacer.